RIGHT THE FIRST TIME
LEARNING Signal Integrity & EMC
SIGNAL INTEGRITY & EMC course on demand at your desk without leaving your workspace ALL FREE
“RIGHT THE FIRST TIME” is a Signal Integrity and Electromagnetic Compliance “how to do it right” class that gives engineers a well-rounded explanation of proper high-speed system design. The course is based on a design methodology developed by a major telecommunications company, which has been documented over multiple years and thousands of designs to produce “right the first time” results 99% of the time. “Right the first time” means the systems work correctly at full speed, they are reliable, they have clearly defined manufacturing margins, and they are quiet enough to pass FCC & CISPR radiated emissions tests… on the first try!
TARGET AUDIENCE: Engineers and CAD Layout Designers responsible for implementing high speed digital and mixed analog digital systems that will work reliably at full speed and still remain quiet enough to pass regulatory EMI tests. The basic methodology upon which this class is based was documented to achieve repeatable first pass success as a standard practice.
WHY SHOULD I DO THIS LEARN
Increasingly fast edge rates in today’s integrated circuits (ICs) cause detrimental high-speed effects, even in PCB designs running at low operating frequencies. As driver ICs switch faster, a growing volume of boards suffers from signal degradation, including over/undershoot, ringing, glitching, crosstalk, and timing problems. When degradation becomes serious enough, the logic on a board can fail.
Any Electrical Engineer, CAD Layout Designer, or Technical Manager tired of design which works now and which do not works after some time, 2 out of 10 board works can get a nightmare whether the next lot of production run is going to work or whether its going to pass FCC & CISPR compliance test would find this class extremely useful. Students who have implemented this methodology have regularly produced complex designs that do indeed work correctly on the first implementation. On average, that saves about $10000 and two months on the average system using 2006 technology. Any financially responsible manager will agree that saving two designs turns on the typical system results in huge savings and potentially even larger profits by getting to market earlier.
FOR PCB AND BOARD Designers
“RIGHT THE FIRST TIME” is delivered together in 2 Parts, Part I and Part II
Basic Signal Integrity including board layer stack-up specification, high-speed routing topology, space, trace, termination practices, and return current control. Get this wrong and the system will reward you with a host of problems including False Clock, False Data, Negative Timing Margins, Clock Jitter, Excessive EMI as well as a host of Manufacturing and Reliability issues.
Power Delivery is a lot more than one 0.1uF and five 0.01uF caps per pin. Power delivery depends upon stack-up, capacitor selection, placement, mounting technique, and quantity. Typical target impedance for memory systems must be around 0.1 ohm from DC to the highest frequency of interest. The highest frequency of interest is most likely in the microwave region. Poor design can result in power delivery impedance poles and inter plane resonance. Many of the mysterious SI and EMI issues can be traced directly to poor power delivery design.
Root causes and cures for EMI. The class’s primary approach is to stop the noise at the source. If noise is eliminated at the source, you do not need to chase it around the board. The recent proliferation of ASIC’s from hell has prompted us to add a section on shielding and filtering. If the problem is in the device, not the board, and you can not find a better behaved substitute for that device, your only choice is to shield and filter.
Single Ended Bus Issues If you have a memory or address bus with both high and low speed devices, do the high speed devices belong close to the processor with the low speed devices farther away, or vice versa? How do you terminate? What about option slots?
How LVDS really works. With the huge noise margin available using LVDS devices, you can use almost any interconnect scheme. However there can be other complications like Cross Talk and EMI if you do it incorrectly.
Giga Bit Serial / SERDES interface routing issues …PCI Express We explain what is important and also debunk some of the popular myths about routing these types of interfaces.
The Analog / Digital Interface i.e. Isolation vs. Communication
Understanding the issues related to “quiet grounds.”
Connectors, Board-to-Board SI, EMI, and Power Issues
Chip Level Package Issues and how to defend against them.
Basic Shielding Theory as it applies to Switching Power Supplies
Critical elements in an effective high-speed system design process. Simply performing a solid pre-layout design review and including the correct personnel can raise you first time odds of success at least 50%. Implementing a full process can result in first time success 99% of the time.
Teaching Method ... Explain, Demonstrate, Do
The instructor will explain the problem and an appropriate method to solve that problem. – Audio & Slides Presentation
The instructor will demonstrate the solution using industry standard software tools. – Audio Video Demonstration
The students will do the work for themselves using lab computers and sample problems.
The students perform computer-based labs to help lock in understanding of the physics behind classical high-speed design problems. This also gives them the freedom to try their own examples. Simply hearing information results in about a 30% retention rate. Seeing a demonstration will raise the retention rate closer 50%. If you actually do the work on something meaningful to the student, the retention is over 80%.
The purpose of this class is not to impress anyone with complex formulae and higher math. There are perfectly good simulators to do the heavy lifting. The purpose is to give layout designers and EE’s the tools to make their next design a quiet, reliable, full speed system on the first try.
You will learn how to
NOTE: All lessons are documented with relevant Screen-shots and Audio-Video demonstration which becomes much easier to kick start & jump on a particular feature to make your learning interesting and easy
Video Demonstrations Details:
Section One: Pre-Layout Analysis
Clock nets must be short of properly terminated to avoid excessive ringing. One consequence of ringing is “input ring-back”. This is when a signal fails to smoothly transition between the input threshold voltages of a receiver. It can result in false switching, meta-stable conditions and timing jitter. A schematic for a simple clock net is created and analyzed. The ring-back is quantified and parallel termination applied to eliminate.
A second consequence of ringing is overshoot. This is when a signal swings past the supply or ground voltage. Excessive overshoot may saturate input transistors, slowing their switching time. In extreme cases it may even permanent damage ICs. A schematic for a second simple clock net is created using an IBIS driver model. The level of overshoot is measured using the typical, fast and slow driver characteristics. Series termination is applied to reduce overshoot.
In the previous chapters a trial and error approach was used to choose termination values. In this chapter the Termination Wizard will be used to pick the optimal values for terminators.
Simulation with parameter sweeping allows you to study the effects of varying design property values. Passive and active component values can be swept, as can PCB geometric values. Sweeping can be used to optimize component values, do sensitivity analysis as well as solution space and reliability analysis. In this chapter a parameter sweeping will be applied to a series terminated net to determine the effect of changing driver strength and termination values.
The TOOL supports two types of EMC analysis: spectrum analysis from current probes and prediction of the far field radiation at a specified point in space. Early detection of major EMC sources using current probes can avoid expensive redesign. In this chapter pre-layout EMC analysis will be demonstrated using a current probe on a net without adequate termination. The termination will be improved and the reduction in EMC.
The examples used in previous chapters were simplified. In this chapter a net that is more typical of real world designs is analyzed. A DDR strobe net is simulated and waveform errors identified. The termination and trace lengths are then optimized to correct the waveform errors
Designing a Multi-Gbps High Speed Serial Channel
High-speed serial channels require more complex signal integrity analysis. In this chapter it will be demonstrated that in the world, more complex does not mean more difficult to use. The chapter starts with the skeleton of a multi-Gbps example net. SPICE driver and load models will be assigned, as will accurate lossy-coupled trace models. The eye opening and BER bathtub curves will be developed for the net with and without transmitter de-emphasis.
Section Two: Post-Layout Analysis
Previous chapters have concentrated on pre-layout analysis. Fixing signal integrity problems early in the design process will provide enormous payback in the minimizing the cost of redesign and lost market opportunity. Even so, compromised are always present in the process of PCB layout and routing, so it is critical that post-layout signal integrity validation be conducted. In this chapter, interactive post-layout analysis will be used to identify a termination issue. The Termination wizard will be used to correct the problem.
Nets on high-density printed circuit boards will be subject to crosstalk from adjacent nets. In this chapter, an example net will be analyzed to establish which adjacent nets inject into it a significant crosstalk voltage. A crosstalk threshold voltage will be set in the TOOL, so it can automatically extract the circuit for a net together with its neighboring nets to which it has strong coupling. The circuit will then be simulated to quantify the level of crosstalk.
Section Three: Additional Topics
PCB Layer Stack-up Editing and Trace Impedance Planning
Creating a good PCB layer stack-up is essential to meet the mechanical, signal and power integrity demands of a design. Trace impedance must be controlled to minimize reflections. Reliable return paths must be provided for signaling currents. Crosstalk must be limited. In addition, there must be adequate power distribution. In this chapter an example PCB layer stack-up will be created. Some of the critical elements of stack-up design will be discussed. Finally trace impedance planning will be done for single ended and differential nets.
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